• WP1 "More Moore"
• WP2 "Beyond CMOS"
• WP3 "Joint Processing Platform"
• WP4 "Modelling and Characterization Platform"
• WP5 "Integration and Spreading of Excellence"

Open positions

OPEN POSITIONS

• 5 PhD Positions at CEA/LETI
• 1 PHD Position at CEA/IEF
• 1 Post Doc Position at Tyndall: Germanium Junctionless Transistors

• Corporate Application Engineer (CAE) position at Synopsys TCAD support

• 1 Post-Doc Position at CEA June 2011: on the theory and modelling of the electronic and transport properties of single impurities in
  nanowire and MOS devices.

• 1 PHD Position at UCL: Towards highly-efficient 10nm MOSFETs
• 1 PHD Position at UCL: New generation of micro and nano systems using metallic glass thin films
• 1 PHD Position at University of Liverpool for the development of AAtomic Layer Deposition of high-k dielectric materials