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November 2011
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Consortium area
SINANO INSTITUTE
Public Area

More Moore (WP1)

Leader:  Prof. Evan Parker, Warwick University (United Kingdom)

 

“More Moore” activities aim to improve CMOS performance for the 22nm node technology and beyond. The outcomes should be applicable both in pushing forward highly scaled devices and as technology boosters that allow longer life to existing geometries.

Joint activity will focus on three areas that can be expected to provide significant impact on the approaches to future CMOS – materials for high speed channels, low access resistance, and high dielectric constant gate stacks. These flagship projects will integrate activities in design, fabrication, characterization and modelling, and be supported in carrying out that work by the Joint Platforms (WP3 & WP4):

  • Flagship Project 1.1 New Channel Materials (coordinated by FZJ)
  • Flagship Project 1.2 Very Low Schottky Barrier MOSFETs (coordinated by ISEN-IEMN)
  • Flagship Project 1.3 Advanced gate stacks/ High k dielectric materials (coordinated by Chalmers)


A fourth activity will provide a forum for discussing hot topics in ultimate CMOS and identifying areas where the partners of this Network can make a contribution (coordinated by GRENOBLE INP-FMNT).