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Consortium area
SINANO INSTITUTE
Public Area

Research activities

The objectives of NANOSIL are to deal with the major technical challenges that face the nanoelectronics industry at the N+4 technology node and beyond, as they are identified by ENIAC, the European Technology Platform for Nanoelectronics (www.eniac.eu). The research activities are therefore focused on the More Moore and Beyond CMOS areas, which compose the two principal workpackages of NANOSIL (WP1 and WP2). They are each composed of Flagship Projects (FSPs) that will address overarching issues related to new materials, new concepts and understandings – and all possessing a modelling component, enabling a full appraisal of potential of these new approaches. WP1 addresses some very advanced ideas to keeping CMOS on the road and would also have relevance in retrofitting to existing technologies. The projects in WP2 are all silicon/SOI-based platforms and represent paradigm shifts from the silicon MOSFET. Urgent appraisal of their technological potential is needed if Europe is to gain a foothold in futuristic solutions.


The FSPs will be executed by accessing the joint processing (WP3) and characterisation and modelling platforms (WP4) that were well established in SINANO. Each of them will be underpinned by Strengthening Projects designed to enhance and further develop existing capabilities.
  
Supporting mobility around the Network and providing training opportunities is invaluable to promoting integration and spread of excellence and is particularly valuable to early stage researchers. WP5 will support and coordinate exchanges and workshops as well as continuing the popular SINANO summer schools. Management (WP6) and scientific co-ordination are essential components for successful joint activity and specific funding has been ring-fenced for this.