• WP1 "More Moore"
• WP2 "Beyond CMOS"
• WP3 "Joint Processing Platform"
• WP4 "Modelling and Characterization Platform"
• WP5 "Integration and Spreading of Excellence"

• For the year 2009:

List of scientific publications and participations to conferences in the year 2009:
nanosil_publications_2009.pdf

• For the year 2008:

- List of scientific publications and participations to conferences in the year 2008:

nanosil_publications_2008.pdf 

• Details of the joint publications with Nanosil aknowledgment:

	Publication
	Workpackage  :  WP4 - Joint Modelling and Characterisation Platform Type  :  Scientific Journal Title  :  Reduced self-heating by strained silicon substrate engineering Title  :  Applied Surface Science Name(s) of participant(s) (conf) and Author(s) (papers)  :  A. O'Neill, S. Olsen, Y. Yang, R. Agaiby, P.-E. Hellstrom, M. Ostling, K. Lyutivitch, E. Kasper, G. Enenman, P. Verheyen, R. Loo, C. Claeys, C. Fiegna, E. Sangiorgi Number / period  :  Vol 254 Year  :  2008 Relevant pages  :  p. 6182 Key words  :  Strained silicon, Self heating, MOSFET Summary  :  Reduced self-heating by strained silicon substrate engineering A. O’Neill a,*, R. Agaiby a, S. Olsen a, Y. Yang a, P.-E. Hellstrom b, M. Ostling b, M. Oehmec, K. Lyutovich c, E. Kasper c, G. Eneman d, P. Verheyen d, R. Loo d, C. Claeys d, C. Fiegna e, E. Sangiorgi e a Newcastle University b Royal Institute of Technology c University of Stuttgart d IMEC e University of Bologna Article history: Accepted 16 February 2008 Available online 16 March 2008 A B S T R A C T Substrate engineering innovations such as SOI and the use of Si/SiGe virtual substrates become necessary in order to maintain performance leverage of integrated circuits with continued scaling. The relevance of thermal effects in device design increases since the thermal conductivity of these new materials is poor. The electrical performance of devices fabricated on thin virtual substrates grown by two different techniques is presented. It is found that self-heating is reduced and that thermal resistance measurements agree with modelling predictions. The reduction in performance enhancement seen in many strained Si MOSFETs is found here to be largely due to self-heating effects, rather than parasitics or the loss of strain. Relative task  :