• WP1 "More Moore"
• WP2 "Beyond CMOS"
• WP3 "Joint Processing Platform"
• WP4 "Modelling and Characterization Platform"
• WP5 "Integration and Spreading of Excellence"

 

• SiNANO BOOK

 

• For the year 2010:

List of scientific publications and participations to conferences in the year 2010:
nanosil_publications_2010.pdf   

• For the year 2009:

List of scientific publications and participations to conferences in the year 2009:
nanosil_publications_2009.pdf

• For the year 2008:

- List of scientific publications and participations to conferences in the year 2008:

nanosil_publications_2008.pdf 

• Details of the joint publications with Nanosil aknowledgment:

	Publication
	Workpackage  :  WP4 - Joint Modelling and Characterisation Platform Type  :  Scientific Journal Title  :  Strained Si/SiGe MOS technology: improving gate dielectric integrity Title  :  Microelectronics Engineering Name(s) of participant(s) (conf) and Author(s) (papers)  :  S. Olsen, L. Yan, R. Agaiby, E. Escobedo-Cousin, A. O'Neill, P.-E. Hellström, M. Ostling, K. Lyutovich, E. Kasper, C. Claeys, E. Parker Number / period  :  - Publisher  :  - Year  :  2008 Key words  :  Si, SiGe, MOSFET, Mobility enhancement, Gate leakage Summary  :  Strained Si/SiGe MOS technology: Improving gate dielectric integrity S.H. Olsen a,*, L. Yan a, R. Agaiby a, E. Escobedo-Cousin a, A.G. O’Neill a, P.-E. Hellström b, M. Östling b, K. Lyutovich c, E. Kasper c, C. Claeys d, E.H.C. Parker e a Newcastle University b KTH Royal Institute of Technology c Stuttgart University d IMEC e University of Warwick Article history: Received 5 September 2007 Received in revised form 7 April 2008 Accepted 13 August 2008 Available online 22 August 2008 A b s t r a c t Strained Si is recognised as a necessary technology booster for the nanoelectronics regime. This work shows that high levels of stress attainable from globally strained Si/SiGe platforms can benefit gate leakage and reliability in addition to MOSFET channel mobility. Device self-heating due to the low thermal conductivity of SiGe is shown to be the dominating factor behind compromised performance gains in short channel strained Si/SiGe MOSFETs. Novel thin virtual substrates aimed at reducing self-heating effects are investigated. In addition to reducing self-heating effects, the thin virtual substrates provide further improvements to gate oxide integrity, reliability and lifetime compared with conventional thick virtual substrates. This is attributed to the lower surface roughness of the thin virtual substrates which arises due to the reduced interactions of strain-relieving misfit dislocations during thin virtual substrate growth. Good agreement between experimental data and physical models is demonstrated, enabling gate leakage mechanisms to be identified. The advantages and challenges of using globally strained Si/SiGe to advance MOS technology are discussed. Relative task  :