Sinano - NANOSIL Partners

For each of the Nanosil Partners, a description of the Institution as well as a presentation of the competences and facilities available can be found (also available as one document ). For further information you can contact the designated team leader.

Short name : WUT	Participant number : 20

Internet homepage : http://www.pw.edu.pl

Adress : Plac Politechniki 1

Postal code : 00-661

Town : Warszawa

Country : Poland

WP1 - More Moore / WP2 - Beyond CMOS / WP4 - Joint Modelling and Characterisation Platform / WP5 - Integration and Spread of Excellence


Brief description of the organization
Institute of Microelectronics and Optoelectronics is a part of the Faculty of Electronics and Information Technology of WUT. It is involved in both education (undergraduate, graduate and Ph.D. studies in the area of Electronics and Information Technology) and research (processing, modeling and characterization of semiconductor devices).

Processing
Facilities/Equipment : • Complete MOS test structure manufacturing line, silicon compatible	Techniques/Competences : • Ultrathin dielectric layers (SiO2, SiON, SiN) formation in very low (<350°C) and standard high temperature processes by means of: • thermal oxidation (>800°C) • plasma oxidation (<100°C) • Ultrashallow implantation (<2nm) (<350°C) • PECVD (<350°C) • Ultrashallow (<2nm) implantation of nitrogen and fluorine • Very low thermal budget MOS test structure technology (particularly suitable for preservation of mechanical stress in the structure and thermal treatment studies)

Characterization & modelling
Facilities/Equipment : • Agilent 4275A (HF-CV) • Agilent 4140B (QS-CV) • Agilent 4285A impedance meter • Keithley SMU236/237 (I-V) • Keithley 617 Ammeter (CP) • Unique pulse generator for CP measurements built in WU	Techniques/Competences : • analysis of MOSFET I-V curves (threshold voltage, subthreshold slope, DIBL, mobility, etc.) • standard CV (also applied to SOI MOS capacitors), gate-leakage current and reliability • analysis of the quality of the semiconductor-gate oxide interface by means of charge pumping (average interface-trap density, energy distribution of trap density) • extraction of generation parameters (surface recombination velocity, generation lifetime) by means of analysis of the electrical characteristics of gated diodes • spectroscopic ellipsometry for independent determination of layer thickness and its optical properties (with the possibility to gain information on chemical composition and physical structure of the layer) • modeling of tunnel currents through high-K gate stacks in single and double gate MOS/SOI diodes and transistors • modeling of electron mobility (drift-diffusion, relaxation time approach) in silicon structures with SiGe layers and high-K gate stacks.